1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and more particularly, to an address latch circuit and a semiconductor memory apparatus using the same.
2. Related Art
In general, a semiconductor memory apparatus operates in synchronization with clock signals. Accordingly, an address signal input to the semiconductor memory apparatus is input in synchronization with the clock signals.
FIG. 1 is a schematic diagram a conventional address latch circuit of a semiconductor memory apparatus. In FIG. 1, an address latch circuit 1 of a semiconductor memory apparatus includes first to third inverters IV1 to IV3, a control inverter IVC1, and first to fourth transistors P1, P2, N1, and N2. The first inverter IV1 receives a clock signal ‘CLK’, and the second inverter IV2 receives an output signal of the first inverter IV1. The first transistor P1 receives the output signal of the first inverter IV1 at a gate terminal thereof and receives an external voltage VDD at a source terminal thereof. The second transistor P2 receives an address signal ‘add’ at a gate terminal thereof and is connected to a drain terminal of the first transistor P1 at a source terminal thereof. The third transistor N1 receives the address signal ‘add’ at a gate terminal thereof and is connected to a drain terminal of the second transistor P2 at a drain terminal thereof. The fourth transistor N2 receives an output of the second inverter IV2 at a gate terminal thereof, is connected to a source terminal of the third transistor N1 at a drain terminal thereof, and is connected to a ground terminal VSS at a source terminal thereof.
The third inverter IV3 has an input terminal which is connected with a node connected to the second transistor P2 and the third transistor N1, and outputs a latch signal ‘latch_s’ at an output terminal thereof. The control inverter IVC1 has an input terminal connected to the output terminal of the third inverter IV3, an output terminal connected to the input terminal of the third inverter IV3, a first control terminal receiving the output signal of the second inverter IV2, and a second control terminal receiving the output signal of the first inverter IV1.
In FIG. 1, the first transistor P1 and the fourth transistor N2 are turned ON when the clock signal ‘CLK’ is at a high level. When the first and fourth transistors P1 and N2 are turned ON, the address signal ‘add’ is inverted and input to the third inverter IV3. The third inverter IV3 inverts the inverted address signal ‘add’ to output it as the latch signal ‘latch_s’.
Conversely, the first and fourth transistors P1 and N2 are turned OFF when the clock signal ‘CLK’ is at a low level. The address signal ‘add’ is not inverted and is not input to the third inverter IV3. However, since the control inverter IVC1 is turned ON when the clock signal ‘CLK’ is at the low level, a latch structure of the third inverter IV3 and the control inverter IVC1 is formed. Accordingly, the latch signal ‘latch_s’ output when the clock signal ‘CLK’ is at the high level is stored by the latch structure of the third inverter IV3 and the control inverter IVC1, thereby maintaining the high level.
In FIG. 1, the address latch circuit continuously operates in synchronization with the clock signals regardless of a change in a state of the semiconductor memory apparatus. For example, when an all-bank precharge command of precharging all banks of the semiconductor memory apparatus is input, all the banks are precharged. In the all-bank precharge state, address information is not required. However, since the address latch circuit continuously operates in synchronization with the clock signals, the address latch circuit generates unnecessary current consumption. In particular, current consumption by the elements IV1, IV2, IVC1, P1, and N2, which are repetitively turned ON and OFF in response to the clock signals shown in FIG. 1, is the largest.